Leakage Current Reduction Using Subthreshold Source-Coupled Logic
نویسندگان
چکیده
منابع مشابه
Reduction of Subthreshold Leakage Current in MOS Transistors
Submitted: Jun 27, 2013; Accepted: Aug 5, 2013; Published: Oct 3, 2013 Abstract: This paper presents a layout technique (double-finger and four-finger) for subthreshold leakage reduction in MOS transistor. NMOS and PMOS when simulated in different layout techniques show considerable reduction in subthreshold leakage and junction leakage currents by the use of double-finger and four-finger techn...
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ژورنال
عنوان ژورنال: IEEE Transactions on Circuits and Systems II: Express Briefs
سال: 2009
ISSN: 1549-7747,1558-3791
DOI: 10.1109/tcsii.2009.2019167